In recent years, due to multiple functioning of mobile phones, digital AV devices, IC cards, and the like, demands have been increasing for downsizing, reduction in thickness, and high integration of semiconductor silicon chips (hereinafter referred to as “chips”). For example, the reduction of thickness is demanded for integrated circuits in which a plurality of chips are integrated, as typified by CSP (chip size package) and MCP (multi-chip package). Among these integrated circuits, a system-in-package (SiP) in which a plurality of semiconductor chips are mounted in a single semiconductor package has become an extremely important technique in order to accomplish downsizing, reduction in thickness, and high integration of chips that are installed in the semiconductor package. The downsizing, reduction in thickness and high integration enables realization of multiple functioning, downsizing, and reduction of weight of electronic devices.
In order to respond to the needs for a thin product, it is required to reduce the thickness of a chip to not more than 150 μm. Further, it is required to process the chip so that its thickness is reduced to not more than 100 μm for the CSP and the MCP, and not more than 50 μm for the IC card.
Conventionally, SiP products are manufactured by use of a method in which respective bumps (electrodes) provided on each of stacked chips are wired to a circuit board by a wire bonding technique. In order to respond to the demand for the reduction in thickness and high integration, a through-hole electrode technique is required, not the wire bonding technique. The through-hole electrode technique is a technique in which (i) chips each having a through-hole electrode are stacked and (ii) a bump is formed on a backside of the chips thus stacked.
A thin chip is manufactured by, for example, in a method as follows: (i) a high purity single crystal silicon or the like is sliced to a wafer form, (ii) a predetermined circuit pattern of an IC or the like is formed on a surface of the wafer by etching the surface of the wafer so that an integrated circuit is built, (iii) a back surface of the semiconductor wafer thus obtained is grinded by use of a grinder, and (iv) after the semiconductor wafer is grinded to a predetermined thickness, the semiconductor wafer is diced so as to form a chip shape. At this time, the predetermined thickness is around a range of 100 μm to 600 μm. Further, in a case where a through-hole electrode is to be formed, the wafer is grinded to a thickness of around a range of 50 μm to 100 μm.
In the manufacture of the semiconductor chip, the semiconductor wafer readily breaks in a case where external force is given to the wafer in the grinding step or at the time when the wafer is carried to the dicing step. This is because the semiconductor wafer is thin and fragile, and because circuit patterns are unlevel. Moreover, in the grinding step, purified water is used to clean the back surface of the semiconductor wafer for removing grinding dust and heat generated at the time of grinding, while grinding process is carried out. At this time, there is the need to prevent contamination of a circuit pattern surface due to the purified water used in cleaning.
Accordingly, in order to protect the circuit pattern surface of the semiconductor wafer and prevent breakage of the semiconductor wafer, a film adhesive for processing is attached on the circuit pattern surface while the grinding process is carried out.
Moreover, at the time of the dicing, the semiconductor wafer is diced in a state in which a protection sheet is attached to a back surface of the semiconductor wafer so that the semiconductor wafer is fixed. Chips obtained by the dicing are pushed up by use of a needle from a film base material side, and are fixed on a die pad.
Known types of film adhesives for processing and protection sheets as such include, for example, ones in which an adhesive layer made of an adhesive composition is provided on a base material film such as polyethylene terephthalate (PET), polyethylene (PE), polypropylene (PP), or ethylene-vinyl acetate copolymer (EVA) (for example, Patent Document 1, Patent Document 2, and Patent Document 3).
An arrangement has also been disclosed (Patent Document 4) in which a protection board is used instead of using the film adhesive for processing or the protection sheet. The protection board is an aluminum nitride-boron nitride pore sintered body impregnated with ladder-type silicone oligomer. In the arrangement, this protection board and the semiconductor wafer are adhered together by use of a thermoplastic film. There is also a method in which a material such as alumina, aluminum nitride, boron nitride, or silicon carbide, each of which has substantially the same thermal expansivity as the semiconductor wafer, is used as the protection board, and thermoplastic resin such as polyimide is used as an adhesive for attaching the protection board to the semiconductor wafer (Patent Document 5). This method suggests applying the adhesive in a form of a film having a thickness in a range of 10 μm to 100 μm. As a method for forming the film, the method of Patent Document 5 suggests that an adhesive composition is applied by spin coating and then dried so that an obtained film has a thickness of not more than 20 μm.
Moreover, due to multilayer interconnection of semiconductor elements, a process is conducted such that: (i) a protection board is adhered, by use of the adhesive composition, to a surface of the semiconductor wafer on which a circuit is formed; (ii) a back surface of the semiconductor wafer is polished; (iii) the back surface thus polished is etched to form a mirror plane; and (iv) a back surface circuit is formed on the mirror plane. In this case, the protection board is adhered to the semiconductor wafer until the back surface circuit is formed (Patent Document 6).
Patent Citation 1
Japanese Patent Application Publication, Tokukai, No. 2003-173993 A (Publication Date: Jun. 20, 2003)
Patent Citation 2
Japanese Patent Application Publication, Tokukai, 2001-279208 A (Publication Date: Oct. 10, 2001)
Patent Citation 3
Japanese Patent Application Publication, Tokukai, No. 2003-292931 A (Publication Date: Oct. 15, 2003)
Patent Citation 4
Japanese Patent Application Publication, Tokukai, N 2002-203821 A (Publication Date: Jul. 19, 2002)
Patent Citation 5
Japanese Patent Application Publication, Tokukai, No. 2001-77304A (Publication Date: Mar. 23, 2001)
Patent Citation 6
Japanese Patent Application Publication, Tokukaisho, No. 61-158145 (Publication Date: Jul. 17, 1986)